Success Stories
Recent Low Power Design Achievements
Success Stories
Case1.
Description
? First 14nm Product
? High performance DSP
? Ultra low power methodology, including multi-power domain, multi-voltage
Application |
HPC DSP |
Process |
14nm 1P11M |
Chip size |
4.2x3.8 sq mm |
Gate count |
10M instance |
Freq. |
>1GHz |
Case2.
Description
? AI Edge usage, 8-core A55 + RISC V core
? High performance processing units
? Up to 8 in 1 chiplet package
? Innovative DFT and physical design method
Application |
AI Edge |
Process |
14nm 1P11M |
Chip size |
10000um x 10000um |
Gate count |
60M instance |
Freq. |
>1.5GHz |
Case3.
Description
? First 40nm SOC production
? ARM A5 core based smart phone solution, high performance for CPU
? Ultra low power methodology, including multi-power domain, multi-voltage
? Complex at speed DFT implementation
Application |
Smart Phone AP + Baseband |
Process |
40nm 1P7M |
Chip size |
4350um x 4300um |
Gate count |
8M instance |
Freq. |
820MHz |
Case4.
Description
? IP: MIPI csi/dsi, HDMI 2.0, USB 3.0, ADC, AFE, PLL, Efuse, LPDDR2/DDR3/LPDDR3
? GPU T720 (2 core): 400Mhz
? Video Codec: 400Mhz
? A53 (4 core): 825Mhz ( no over-drive)
? DDR: 800Mhz
Application |
Application Processor |
Process |
28nmPS 1P8M |
Chip size |
8000um x 8500um |
Gate count |
8M instance |
Freq. |
>1GHz |
Case5.
Description
? Dual core high performance CPU
? 72bit DDR with ECC
? Power
? A53 (4 core): 825Mhz ( no over-drive)
? A53: use ARM PoP 12T library
? DDR: 800Mhz
Application |
CPU |
Process |
40nm 1P9M |
Chip size |
9000um x 10400um |
Gate count |
8.5M instance |
Freq. |
800MHz |